1. Field of Invention
The present invention relates to a method for manufacturing a capacitor for a semiconductor device. More particularly, the present invention relates to the manufacturing of a capacitor for a dynamic random access memory (DRAM) cell.
2. Description of Related Art
DRAMs use an array of capacitors fabricated on a semiconductor substrate to store digital data. In general, the charge storage states are utilized to store a bit of data. Normally, a capacitor with charges is regarded as in a logic "1" state, and a capacitor without stored charges is regarded as in a logic "0" state. Hence, a single bit of binary data is stored in a capacitor. The charge storage capacity of a capacitor depends on several factors including surface area within the electrode of a capacitor, the reliability of the electrode isolation and the dielectric constant of the dielectric layer between the electrodes of a capacitor. Storage and retrieval of data to and from memory as well as reading and writing operations are executed by the transfer of charges to or from the capacitor through a transfer field effect transistor (FET), which is coupled to a bit line. The bit line is connected to one source/drain terminal of the transfer FET, while the charge storage capacitor is connected to the other source/drain terminal of the transfer FET. A word line is connected to the gate of the transfer FET. Control signals can then be sent through the word line to the gate of the transfer FET, thereby switching open the transistor. Hence, an electrical connection between one electrode of the capacitor and the bit line is established, and the transfer of charges to and from the capacitor is allowed.
To increase data storage capacity of memory in a single chip, one method is to increase its density. High-density memory not only can provide a compact structural design on a wafer, but can also save production cost. In general, the density of an integrated circuit device can be increased by reducing the wiring lines, the dimensions of a transistor gate or area occupation of a device isolation region. However, the reduction in dimensions for some circuit elements is always limited by some newly established set of design rules because of miniaturization.
FIG. 1 is an equivalent circuit diagram of a DRAM unit. A DRAM unit comprises a transfer transistor T and a storage capacitor C. The source terminal of a transfer transistor T is connected to a bit line BL, and the drain terminal is connected to a storage electrode of a storage capacitor C. The gate terminal of the transfer transistor is connected to a word line WL. The opposed electrode 12 is connected to a fixed voltage source. A dielectric layer 14 is formed between the storage electrode 10 and the opposed electrode 12.
In order to increase the surface area of the lower electrode of a capacitor, various methods of fabricating uneven surface structures are invented including, for example, crown-shaped, pillar-shaped, fin-shaped, a tree-trunk with branches or a cavity structure. In addition, a hemispherical grained silicon (HSG-Si) layer can be formed over the surface of an electrode to increase the charge storage capacity of a capacitor up to about 80 percent. However, the capacitance of a capacitor can still be increased by following an improved method of manufacturing.